A phase regulating arrangement of the generic type is shown, for example, in the document U.S. Pat. No. 5,648,744. Said document shows an oscillator having a plurality of frequency bands which can be enabled and disabled and can each be tuned. In this case, the subband is selected by measuring the voltage at the loop filter, that is to say at the input of the oscillator and at the output of the phase detector, and increasing or decreasing the frequency band if certain limits are undershot or overshot.
Phase regulating circuits are also referred to as PLLs (Phase-Locked Loops).
In this case, following frequency division, a phase detector is normally used to compare the output signal of an oscillator with a reference signal, and a loop filter is used to tune the controllable oscillator in a manner dependent on the phase comparison.
Such phase-locked control loops are usually used to synthesize signals at a desired frequency or, for example, to recover a clock signal from a data stream. Phase-locked loops can also be advantageously used in mobile radio for the purposes of signal modulation.
The oscillator of the phase-locked loop is normally of voltage-controlled design in the form of a so-called VCO (Voltage-Controlled Oscillator) which generates an output frequency fVCO that is dependent on an input control voltage Vc. This voltage is also referred to as the tuning voltage. The quotient of the change in the output frequency ΔfVCO with respect to the change in the control voltage ΔVC is referred to as the slope KV of the oscillator and determines the characteristic curve of the latter. The slope may therefore be described by the formula:
      K    V    =                    Δ        ⁢                                  ⁢                  f          vco                            Δ        ⁢                                  ⁢                  V          C                      .  
The output frequency of a VCO is composed of a variable component fvar, which is determined by the slope and the control voltage, and a fixed component, the so-called fundamental frequency fB, which is determined by the dimensioning of the VCO. The output frequency fVCO therefore results from the equation:fVCO=fB+fVAR=fB+KV*VC.
Since the fundamental frequency is subject to severe fluctuations owing to manufacturing tolerances and process variations during production of the VCO using integrated circuit technology, the variable component fvar must be large enough to be able to achieve all of the target frequencies despite the tolerances of the fundamental frequency. This may, of course, be ensured with a sufficiently large KV, that is to say with a steep slope, but has the disadvantage that it increases the sensitivity of the PLL to noise and sidetones. This is problematic, in particular, in large scale integrated circuits since interference from other circuit blocks may be coupled over into the VCO via common supply voltages and a common substrate.
One solution to this problem is achieved, in the prior art document mentioned initially, by providing a VCO having subbands which can be changed over and can each be tuned. In this case, the desired frequency range is covered with a plurality of frequency bands instead of with only one single frequency band. In this case, in a first step, the VCO is set in such a manner that the desired frequency is approximately achieved. In a second step, the tuning voltage VC is then used to pull the VCO to the exact frequency within a selected subband. This results in the advantage that the slope of the VCO is relatively gentle within the individual subbands, with the result that the above-described problems of noise and coupling-over are avoided. This solution is particularly well suited to large scale integrated circuits using complementary MOS or BiCMOS circuit technology since the entire measurement and regulating logic can be accommodated in a current-saving and space-saving manner on one chip.
The paper by Y. Koo et al.: “A Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems”, Journal of Solid-State Circuits, Vol. 37, No. 5, May 2002, pp. 536–542, describes a circuit, in which the control signal for selecting the desired subbands of the VCO is tapped off at the phase detector. In this case, the edges of the reference signal and the divided-down VCO signal are counted and compared at the phase detector.
The two circuits described have the principle in common that a variable that is derived from the VCO frequency is measured and not the oscillator frequency itself. On the one hand, this is associated with the disadvantage that the VCO frequency at the phase detector has already been reduced by the divider factor n of the frequency divider, as a result of which the frequency resolution has been reduced or the measurement time required has been increased. In addition, further analog circuit blocks for signal processing are required when measuring analog variables such as the loop filter voltage. Furthermore, when the PLL is operated as a so-called fractional N frequency synthesizer, the divider factor N is varied once per reference period. The systematic error caused thereby must be taken into account in a complex manner during regulation.
Programmable dividers for high frequencies are normally always in the form of dual-modulus dividers or multi-modulus dividers for reasons of speed.
Such a programmable frequency divider is specified, for example, in the document C. S. Vaucher et al.: “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35 μm CMOS Technology”. This paper reveals that programmable radiofrequency dividers cannot be read directly.
In the document U.S. Pat. No. 5,182,528, the frequency of the oscillator is determined using a frequency counter. A microcomputer supplies the digital control signals and the analog control voltage via a complex digital/analog converter for the VCO. The document describes how a separate computer is required for the complicated driving and reading of the VCO. In addition, the circuit is not suitable as a frequency synthesizer that meets high demands in terms of the phase noise, as are required, however, for mobile radio systems such as GMS (Global System for Mobile Communication) or UTMS (Universal Mobile Telecommunication System). Furthermore, in the document described, no real phase comparison but rather merely a frequency comparison is carried out. The architectures of the other documents which have already been explained attempt to circumvent this complicated operation of reading out the high frequency at the output of the oscillator just by determining the output frequency of the VCO at the phase detector.
The document A. Kral, F. Behbahani and A. A. Abidi “RF-CMOS Oscillators With Switched Tuning” also shows a VCO having subbands which can be changed over.
The document EP 1 189 347 A1 shows a voltage-controlled oscillator having a capacitance bank. Control is effected, inter alia, using a digital signal processor having a frequency measuring device, which is connected to the VCO output via a frequency divider.